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  1. Home
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  3. Technology & IT Infrastructure
  4. Graduate Design Engineer 2022

Graduate Design Engineer 2022

Lock Applications for this job are now closed
DEADLINE 14th April 2022
Graduate job
Xilinx
Cambridge | Northern Ireland
Technology & IT Infrastructure

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx NI is seeking a Graduate / Junior Design Engineer to assist with the development of FPGA-based hardware and embedded software platforms for Data Centre acceleration applications. This is an exciting position working on the latest FPGA hardware and software technologies from Xilinx, including Vivado Design Suite, Versal ACAP devices and Alveo data center boards using the Vitis unified software platform.

Technical Skills

  • VHDL/Verilog ASIC and FPGA design
  • Familiarity with Xilinx FPGA and system design tools preferred
  • Familiarity with scripting languages: Tcl, Python, Perl preferred
  • Familiarity with SystemVerilog would be an advantage
  • Excellent communication, teamwork & problem-solving skills

Qualifications

  • Degree or better in Electronic Engineering, Computer science, or related subject
DEADLINE 14th April 2022

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